 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| RF2140 2 Typical Applications * 3V DCS1800 (PCN) Cellular Handsets * 3V DCS1900 (PCS) Cellular Handsets * 3V Dual-Band/Triple-Band Handsets * Commercial and Consumer Systems * Portable Battery-Powered Equipment * GPRS Compatible 3V DCS POWER AMPLIFIER 2 POWER AMPLIFIERS Product Description The RF2140 is a high power, high efficiency power amplifier module offering high performance in GSM or GPRS applications. The device is manufactured on an advanced GaAs HBT process, and has been designed for use as the final RF amplifier in DCS1800/1900 hand held-digital cellular equipment and other applications in the 1700MHz to 2000MHz band. On-board power control provides over 65dB of control range with an analog voltage input, and provides power down with a logic "low" for standby operation. The device is self-contained with 50 input and the output can be easily matched to obtain optimum power and efficiency characteristics.The RF2140 can be used together with the RF2138 for dual-band operation. The device is packaged in an ultra-small ceramic package, minimizing the required board space. Optimum Technology Matching(R) Applied Si BJT Si Bi-CMOS 3.50 3.35 sq. 1 1.50 1.20 0.38 0.40 sq. R F2 17 4 2.00 4.20 sq. 3.95 1.50 sq. ALL SOLDER PAD TOLERANCES P0.05mm 0.28 0.80 0.13 P ro du c t Package Style: MP16K01A u GaAs HBT SiGe HBT GaAs MESFET Si CMOS Features * Single 2.7V to 4.8V Supply Voltage * +33dBm Output Power at 3.5V * 27dB Gain with Analog Gain Control * 51% Efficiency * 1700MHz to 1950MHz Operation * Supports DCS1800 and PCS1900 1 AT_EN 2 RF IN 3 GND1 4 5 16 15 ee U pg r 6 7 APC2 8 VCC ad ed VCC2 14 13 12 RF OUT 11 RF OUT 10 RF OUT 9 2F0 NC GND2 VCC2 VCC2 VCC1 APC1 Ordering Information RF2140 RF2140 PCBA 3V DCS Power Amplifier Fully Assembled Evaluation Board S Functional Block Diagram RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Rev A12 011031 2-129 RF2140 Absolute Maximum Ratings Parameter Supply Voltage Power Control Voltage (VAPC) Enable Voltage (VAT_EN) DC Supply Current Input RF Power Duty Cycle at Max Power Output Load VSWR Operating Case Temperature Storage Temperature Rating -0.5 to +6.0 -0.5 to +3.0 -0.5 to +3.0 1500 +13 50 10:1 -40 to +85 -55 to +150 Unit VDC V V mA dBm % C C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). 2 POWER AMPLIFIERS Parameter Specification Min. Typ. Max. Unit Condition Temp=25 C, VCC =3.5V, VAPC1,2 =2.6V, VAT_EN =2.6V, PIN =+6dBm, Freq=1710MHz to 1910MHz, 25% Duty Cycle, pulse width=1154s See application schematic for tuning details. A different tuning is required. Temp=25 C, VCC =3.5V, VAPC1,2 =2.6V Temp=+25 C, VCC =3.2V, VAPC1,2 =2.6V Temp=+85 C, VCC =3.2V, VAPC1,2 =2.6V Temp=25 C, VCC =2.7V, VAPC1,2 =2.6V Temp=+85 C, VCC =2.7V, VAPC1,2 =2.6V At POUT,MAX, VCC =3.5V At POUT,MAX, VCC =3.0V POUT =+20dBm POUT =+10dBm Overall Operating Frequency Range Usable Frequency Range Maximum Output Power 1710 to 1785 1850 to 1910 1700 to 2000 +33 +32.8 +31.5 +31 +30 51 51 15 10 +7 MHz MHz MHz dBm dBm dBm dBm dBm % % % % dBm dBm +32 +31.5 Total Efficiency P Recommended Input Power Range Output Noise Power +5 ro du ct +9 -79 -30 -35 -45 -50 -45 -45 -45 -36 2.2:1 3:1 +29.5 45 Forward Isolation Second Harmonic Third Harmonic Fourth Harmonic Fifth Harmonic Sixth Harmonic All Other Non-Harmonic Spurious Input Impedance Input VSWR ad ed S ee U pg r -37 -40 -60 -65 -50 -50 -50 50 Output Load VSWR Output Load Impedance 10:1 4.5-j3.9 2-130 R F2 17 dBm dBm dBc dBc dBc dBc dBc dBm RBW=100kHz, 1805MHz to 1880MHz and 1930MHz to 1990MHz, POUT,MIN Rev A12 011031 RF2140 Parameter Power Control Power Control "ON" Power Control "OFF" Attenuator Enable "ON" Attenuator Enable "OFF" Power Control Range Gain Control Slope APC Input Capacitance APC Input Current AT_EN Input Current Turn On/Off Time 0.2 2.5 0.2 62 0.5 2.6 0.5 68 100 4.5 10 5 10 500 10 100 2.6 V V V V dB dB/V pF mA A A A ns V V V Maximum POUT, Voltage supplied to the input Minimum POUT, Voltage supplied to the input For maximum isolation when VAPC is low For power down mode VAPC1,2 =0.2V to 2.6V, VAT_EN =2.6V, PIN =+10dBm POUT =-10dBm to +33dBm DC to 2MHz VAPC1,2 =2.6V VAPC1,2 =0V VAT_EN =2.6V, VAPC1,2 =0V VAT_EN =0V, VAPC1,2 =0V Specification Min. Typ. Max. Unit Condition 2.85 2 POWER AMPLIFIERS Power Supply 2.7 Power Supply Current 55 1.3 1 1 295 10 10 Rev A12 011031 S ee U pg r ad ed P ro du ct R F2 17 A mA A A 4.8 5.5 4 Power Supply Voltage 3.5 Specifications Nominal operating limits, POUT <+33dBm With maximum output load VSWR 6:1, POUT <+33dBm DC Current at POUT,MAX Idle Current, PIN <-30dBm PIN <-30dBm, VAPC1,2 =0.2V PIN <-30dBm, VAPC1,2 =0.2V, Temp=+85 C 2-131 RF2140 Pin 1 Function GND2 Description Ground connection for the driver stage. Keep traces physically short and connect immediately to the ground plane for best performance. It is important for stability that this pin has it's own vias to the groundplane, to minimize any common inductance. This pin is internally connected to the ground slug. Control input for the PIN diode. The purpose of the PIN diode is to attenuate the RF input drive level when the VAPC is low. This serves both to reduce the leakage through the device cause by self biasing when driving with high level at the RF input, as well as to maintain a good input match when the bias of the input stage is turned off. When this pin is "high" the PIN diode control is turned on. See the Theory of Operation for more details. RF Input. This is a 50 input, but the actual impedance depends on the interstage matching network connected to pin 5. An external DC blocking capacitor is required if this port is connected to a DC path to ground or a DC voltage. Interface Schematic See pin 15. 2 POWER AMPLIFIERS 2 AT_EN To PIN diode 2 k AT_EN GND1 VCC1 3 RF IN RF IN PIN From Attn control circuit GND 1 From Bias Stages 5 VCC1 ro du ct 6 APC1 R F2 17 4 4 GND1 P Ground connection for the pre-amplifier stage. Keep traces physically See pin 3. short and connect immediately to the ground plane for best performance. It is important for stability that this pin has it's own vias to the groundplane, to minimize any common inductance. Power supply for the pre-amplifier stage and interstage matching. This See pin 3. pin forms the shunt inductance needed for proper tuning of the interstage match. Please refer to the application schematic for proper configuration, and note that position and value of the components are important. Power Control for the driver stage and pre-amplifier. When this pin is APC VCC "low," all circuits are shut off. A "low" is typically 0.5V or less at room temperature. A shunt bypass capacitor is required. During normal operation this pin is the power control. Control range varies from about 1.0V for -10dBm to 2.6V for +33dBm RF output power. The maximum power that can be achieved depends on the actual output matching; see the application information for more details. The maximum current into this pin is 5mA when VAPC1 =2.6V, and 0mA when VAPC =0V. GND GND To RF Stages 7 8 9 10 APC2 VCC NC RF OUT Power Control for the output stage. See pin 6 for more details. Power supply for the bias circuits. Not connected. Connect this pin to the ground plane for compatibility with future packages. RF Output and power supply for the output stage. Bias voltage for the final stage is provided through this wide output pin. An external matching network is required to provide the optimum load impedance. ad ed See pin 6. See pin 6. U pg r RF OUT 11 12 13 S ee From Bias GND Stages PCKG BASE RF OUT RF OUT 2F0 Same as pin 10. Same as pin 10. Connection for the second harmonic trap. This pin is internally connected to the RF OUT pins. The bonding wire together with an external capacitor form a series resonator that should be tuned to the second harmonic frequency in order to increase efficiency and reduce spurious outputs. Same as pin 15. Same as pin 10. Same as pin 10. Same as pin 10. 14 2-132 VCC2 Rev A12 011031 RF2140 Pin 15 Function VCC2 Description Power supply for the driver stage and interstage matching. This pin forms the shunt inductance needed for proper tuning of the interstage match. Please refer to the application schematic for proper configuration, and note that position and value of the components are important. Same as pin 15. Ground connection for the output stage. This pad should be connected to the groundplane by vias directly under the device. A short path is required to obtain optimum performance, as well as to provide a good thermal path to the PCB for maximum heat dissipation. Interface Schematic VCC2 From Bias GND2 Stages Rev A12 011031 S ee U pg r ad ed P ro du ct R F2 17 4 2-133 POWER AMPLIFIERS 16 Pkg Base VCC2 GND Same as pin 15. 2 RF2140 Theory of Operation and Application Information The RF2140 is a three-stage device with 28 dB gain at full power. Therefore, the drive required to fully saturate the output is +5dBm. Based upon HBT (Heterojunction Bipolar Transistor) technology, the part requires only a single positive 3V supply to operate to full specification. Power control is provided through a single pin interface, with a separate Power Down control pin. The final stage ground is achieved through the large pad in the middle of the backside of the package. First and second stage grounds are brought out through separate ground pins for isolation from the output. These grounds should be connected directly with vias to the PCB ground plane, and not connected with the output ground to form a so called "local ground plane" on the top layer of the PCB. The output is brought out through the wide output pad, and forms the RF output signal path. The amplifier operates in near Class C bias mode. The final stage is "deep AB", meaning the quiescent current is very low. As the RF drive is increased, the final stage self-biases, causing the bias point to shift up and, at full power, draws about 1500mA. The optimum load for the output stage is approximately 4.5. This is the load at the output collector, and is created by the series inductance formed by the output bond wires, vias, and microstrip, and 2 shunt capacitors external to the part. The optimum load impedance at the RF Output pad is 4.5-j3.9. With this match, a 50 terminal impedance is achieved. The input is internally matched to 50 with just a blocking capacitor needed. This data sheet defines the configuration for GSM operation. VCC RF IN 750 5 k APC 2 k AT_EN 500 PIN From Bias Stages 2 POWER AMPLIFIERS The current through the PIN diode is controlled by two signals: AT_EN and APC. The AT_EN signal allows current through the PIN diode and is an on/off function. The APC signal controls the amount of current through the PIN diode. Normally, the AT_EN signal will be derived from the VCO ENABLE signal available in most GSM handset designs. If maximum isolation is needed before the ramp-up, the AT_EN signal needs to be turned on before the RF power is applied to the device input. The current into this pin is not critical, and can be reduced to a few hundred micro amps with an external series resistor. Without the resistor, the pin will draw about 700A. ad ed P When the device is driven at maximum input power self biasing would occur. This results in less isolation than one would expect, and the maximum output power would be about -15dBm. If the drive power to the PA is turned on before the GSM ramp-up, higher isolation is required. In order to meet the GSM system specs under those conditions, a PIN diode attenuator connected to the input can be turned on. The figure below shows how the attenuator and its controls are connected. U pg r The input is DC coupled; thus, a blocking cap must be inserted in series. Also, the first stage bias may be adjusted by a resistive divider with high value resistors on this pin to VPC and ground. For nominal operation, however, no external adjustment is necessary as internal resistors set the bias point optimally. S ee 2-134 ro du ct Because of the inverting stage at the APC input, the current through the PIN diode is inverted from the APC voltage. Thus, when VAPC is high for maximum output power, the attenuator is turned off to obtain maximum drive level for the first RF stage. When VAPC is low for maximum isolation, the attenuator is be turned on to reduce the drive level and to avoid self-biasing. The PIN diode is dimensioned such that a low VAPC the impedance of the diode is about 50 Ohm. Since the input impedance of the first RF stage become very high when the bias is turned off, this topology will maintain a good input impedance over the entire VAPC control range. VCC1 and VCC2 provide supply voltage to the first and second stage, as well as provides some frequency selectivity to tune to the operating band. Essentially, Rev A12 011031 R F2 17 4 RF2140 the bias is fed to this pin through a short microstrip. A bypass capacitor sets the inductance seen by the part, so placement of the bypass cap can affect the frequency of the gain peak. This supply should be bypassed individually with 100pF capacitors before being combined with VCC for the output stage to prevent feedback and oscillations. The RF OUT pin provides the output power. Bias for the final stage is fed to this output line, and the feed must be capable of supporting the approximately 1.5A of current required. Care should be taken to keep the losses low in the bias feed and output components. A narrow microstrip line is recommended because DC losses in a bias choke will degrade efficiency and power. While the part is safe under CW operation, maximum power and reliability will be achieved under pulsed conditions. The data shown in this data sheet is based on a 12.5% duty cycle and a 600s pulse, unless specified otherwise. The part will operate over a 3.0V to 5.0V range. Under nominal conditions, the power at 3.5V will be greater than +32dBm at +85C. As the voltage is increased, however, the output power will increase. Thus, in a system design, the ALC (Automatic Level Control) Loop will back down the power to the desired level. This must occur during operation, or the device may be damaged from too much power dissipation. At 5.0V, over +36dBm may be produced; however, this level of power is not recommended, and can cause damage to the device. To avoid excessively high currents it is important to control the VAPC when operating at supply voltages higher than 4.0V, such that the maximum output power is not exceeded. 2 POWER AMPLIFIERS High current conditions are potentially dangerous to any RF device. High currents lead to high channel temperatures and may force early failures. The RF2140 includes temperature compensation circuits in the bias network to stabilize the RF transistors, thus limiting the current through the amplifier and protecting the devices from damage. The same mechanism works to compensate the currents due to ambient temperature variations. Rev A12 011031 S ee U pg r The HBT breakdown voltage is >20V, so there is no issue with overvoltage. However, under worst-case conditions, with the RF drive at full power during transmit, and the output VSWR extremely high, a low load impedance at the collector of the output transistors can cause currents much higher than normal. Due to the bipolar nature of the devices, there is no limitation on the amount of current the device will sink, and the safe current densities could be exceeded. ad ed P ro du ct R F2 17 4 2-135 RF2140 Application Schematic Instead of a stripline an inductor of ~6 nH can be used VCC 15pF Very close to pin 15/16 VCC2 VCC2 2F0 1.0 pF 13 12 RF OUT 3 15 pF GND1 4 5 VCC1 APC1 6 APC2 7 VCC 8 NC 10 9 VCC 15 pF 11 5.1 pF Note 1 1.0 pF Note 1 15 pF Instead of a stripline an Quarter wave inductor can be length used 50 strip 15 pF RF OUT VCC 1 nF GND2 VCC2 16 2 POWER AMPLIFIERS 1 AT_EN AT_EN RF IN RF IN 2 15 14 15 pF 15 pF APC 15 pF Note: All capacitors are standard 0402 multi layer chip Note 1: Using a hi-Q capacitor will increase efficiency slightly Internal Schematic VCC1 VCC2 RF OUT ad ed P ro du ct APC1 R F2 17 VCC APC2 VCC 200 2.5k 1.5k GND2 Distance between 3.9 edge of device and capacitor is VCC 0.240" to improve the "off" isolation RF IN 750 VCC 500 500 U pg r 320 5k APC1 2k AT_EN 2.5k S ee 1.5k GND1 PKG BASE 2-136 4 Rev A12 011031 Distance between edge of device and capacitor is 0.080" Distance center to center of capacitors is 0.220" RF2140 Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) P1-1 C22 1nF P1-3 Schematic 2140400 Rev A Board 2140410 Rev A C6 1 nF C19 3.3 F C5 * 12pF C25 C9 33 pF C8 1 nF C7 3.3 F 2 POWER AMPLIFIERS GND2 VCC2 VCC2 VCC2 2F0 C21 1nF R3 0 C10 * 0.9 pF 13 12 RF OUT 11 10 package edge to inside C3 .050" 1 AT_EN 2 RF IN 3 16 15 14 Quarter wave length 50 strip .150" C23** C3** C24** C2 33 pF C4** J1 RF IN C1 33 pF R1 3.9 J2 RF OUT GND1 4 5 VCC1 APC1 6 APC2 7 VCC 8 NC Capacitors are 0402. *Murata GRM36COG series ** Johanson 500R07F series All others are Panasonic ECU series C13 33 pF C14 33 pF C15 33 pF C20 3.3 F P1-3 Band DCS PCS C3 (pF) 5.1 3.9 C4 (pF) 1.8 1.2 C23 (pF) N/I 0.5 C24 (pF) N/I 0.6 Rev A12 011031 S ee U pg r ad ed P ro du ct C25 (pF) N/I 0.5 C16 1 nF J3 VAPC C17 1 nF R F2 17 P1-1 1 2 3 C18 3.3 F P1-3 P1-3 C12 1 nF C11 33 pF 9 4 ENABL GND VCC P1 2-137 RF2140 Evaluation Board Layout Board size 2.0" x 2.0" Board Thickness 0.014"; Board Material FR-4; Multi-Layer 2 POWER AMPLIFIERS 2-138 S ee U pg r ad ed P ro du ct R F2 17 Rev A12 011031 4 RF2140 Typical Test Setup Power Supply V- S- S+ V+ 2 POWER AMPLIFIERS RF Generator 3dB Buffer x1 OpAmp Puls Generator A buffer amplifier is recommended because the current into the Vapc changes with voltage. As an alternative, the voltage may be monitored with an oscilloscope. Notes about testing the RF2140 The test setup shown above includes two attenuators. The 3dB pad at the input is to minimize the effects that the switching of the input impedance of the PA has on the signal generator. When Vapc is switched quickly, the resulting input impedance change can cause the signal generator to vary its output signal, either in output level or in frequency. Instead of an attenuator an isolator may also be used. The attenuator at the output is to prevent damage to the spectrum analyzer, and should be able to handle the power. It is important not to exceed the rated supply current and output power. When testing the device at higher than nominal supply voltage, the VAPC should be adjusted to avoid the output power exceeding +36dBm. During load-pull testing at the output it is important to monitor the forward power through a directional coupler. The forward power should not exceed +36dBm, and VAPC needs to be adjusted accordingly. This simulates the behavior for the power control loop in this respect. To avoid damage, it is recommended to set the power supply to limiting the current during the burst, not to exceed the maximum current rating. Rev A12 011031 S ee U pg r ad ed P ro du ct R F2 17 10dB/5W 4 Spectrum Analyzer 2-139 2 POWER AMPLIFIERS 2-140 RF2140 S ee U pg r ad ed P ro du ct R F2 17 4 Rev A12 011031 |
Price & Availability of RF2140PCBA
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |